What Is a Mips Read Before Write Data Hazard?

12 Treatment Information Hazards

Dr A. P. Shanthi

The objectives of this module are to hash out how data hazards are handled in full general and also in the MIPS architecture.

We have already discussed in the previous module that true information dependences give rise to RAW hazards and name dependences (antidependence and output dependence) give rising to WAR hazards and WAW hazards, respectively.

Figure 12.1 gives a situation of having true data dependences. The use of the result of the ADD education in the side by side three instructions causes a hazard, since the register is not written until later those instructions read it. The write back for the Add instruction happens only in the 5th clock cycle, whereas the next three instructions read the register values before that, and hence will read the incorrect data. This gives rise to RAW hazards.

One effective solution to handle true data dependences is forwarding. Forwarding is the concept of making information bachelor to the input of the ALU for subsequent instructions, fifty-fifty though the generating instruction hasn't gotten to WB in order to write the memory or registers. This is also chosen brusk circuiting or by passing. This is illustrated in Figure 12.2.

The first instruction has finished execution and the result has been written into the EX/MEM buffer. And so, during the fourth clock cycle, when the second educational activity, SUB needs data, this can be forwarded from the EX/MEM buffer to the input of the ALU. Similarly, for the next AND instruction, the result of the first instruction is at present available in the MEM/WB buffer and can exist forwarded from there. For the OR instruction, the consequence is written into the register file during the kickoff half of the clock cycle and the data from at that place is read during the 2nd half. So, this pedagogy has no trouble. In short, data volition have to be forwarded from either the EX/MEM buffer or the MEM/WB buffer.

Effigy 12.three shows the hardware changes required to support forwarding. The inputs to the ALU take increased. The multiplexors will accept to exist expanded, in guild to accommodate the boosted inputs from the two buffers.

Figure 12.four shows a case where the first instruction is a load and the information becomes available just after the fourth clock bike. And so, forwarding will not help and the 2d instruction will anyway have a stall of one bike. For the side by side instruction, AND, data is forwarded from the MEM/WB buffer. There are thus instances where stalls may occur even with forwarding. However, forwarding is helpful in minimizing hazards and sometimes in totally eliminating them.

The other method of fugitive / minimizing stalls due to true data dependences is to reorder the code – separate the dependent instructions. This is illustrated in Figure 12.5. The snippet shown calculates A = B + E; C = B + F; The dependent pedagogy after the load can be reordered to avoid use of load event in the next pedagogy. This reordering has helped in reducing the number of clock cycles for execution from 13 to 11. 2 stalls have been avoided.

Based on the give-and-take given earlier, we tin can place the 2 pairs of take a chance conditions equally:

1a. EX/MEM.RegisterRd = ID/EX.RegisterRs

1b. EX/MEM.RegisterRd = ID/EX.RegisterRt

2a. MEM/WB.RegisterRd = ID/EX.RegisterRs

2b. MEM/WB.RegisterRd = ID/EX.RegisterRt

The note used here is as follows: The get-go office of the name, to the left of the period, is the name of the pipeline register and the 2d part is the name of the field in that register. For example, "ID/EX.RegisterRs" refers to the number of one register whose value is found in the pipeline annals ID/EX; that is, the one from the first read port of the annals file. We shall hash out the various hazards based on the post-obit sequence of instructions.

The showtime hazard in the sequence is on register $two, between the result of sub $2,$1,$three and the first read operand of and $12,$ii,$5. This chance tin exist detected when the and instruction is in the EX stage and the prior instruction is in the MEM stage, so this is hazard 1a: EX/MEM.RegisterRd = ID/EX.RegisterRs = $two

The sub-or is a type 2b hazard:

MEM/WB.RegisterRd = ID/EX.RegisterRt = $2

The two dependences on sub-add are not hazards because the annals file supplies the proper information during the ID stage of add. There is no data risk betwixt sub and sw considering sw reads $2 the clock bicycle afterward sub writes $2. Yet, equally some instructions do not write into the annals file, this rule has to exist modified. Otherwise, sometimes information technology would forward when it was unnecessary. One solution is simply to check to run across if the RegWrite signal will be active. Examining the WB command field of the pipeline annals during the EX and MEM stages determines if RegWrite is asserted or not. Also, MIPS requires that every utilise of $0 equally an operand must yield an operand value of naught. In the result that an education in the pipeline has $0 as its destination (for example, sll $0, $one, 2), we want to avoid forwarding its maybe nonzero issue value. The conditions to a higher place thus work properly as long as nosotros add together EX/MEM.RegisterRd ≠ 0 to the showtime gamble status and MEM/WB.RegisterRd ≠ 0 to the second.

Figure 12.6 shows the forwarding paths added to the MIPS pipeline. The ForwardA and ForwardB are the additional control signals added. These control signals take on a value of 00, 10 or 01, depending on whether the multiplexor volition pass on the data from the ID/EX, EX/MEM or MEM/WB buffers, respectively.

The weather condition for detecting hazards and the control signals to resolve them are equally follows:

1. EX chance:

if (EX/MEM.RegWrite

and (EX/MEM.RegisterRd _ 0)

and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10

if (EX/MEM.RegWrite

and (EX/MEM.RegisterRd _ 0)

and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10

This case forrad the event from the previous instruction to either input of the ALU. If the previous instruction is going to write to the register file and the write register number matches the read register number of ALU inputs A or B, provided it is not register 0, and so straight the multiplexor to selection the value instead from the pipeline register EX/MEM.

ii. MEM hazard:

if (MEM/WB.RegWrite

and (MEM/WB.RegisterRd _ 0)

and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01

if (MEM/WB.RegWrite

and (MEM/WB.RegisterRd _ 0)

and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01

As mentioned above, there is no hazard in the WB stage because we assume that the register file supplies the right result if the instruction in the ID stage reads the aforementioned register written by the educational activity in the WB stage. Such a register file performs another form of forwarding, merely it occurs within the annals file.

Another complication is the potential data hazards between the upshot of the instruction in the WB stage, the result of the instruction in the MEM stage, and the source operand of the instruction in the ALU phase. For example, when summing a vector of numbers in a single register, a sequence of instructions volition all read and write to the same annals equally indicated below:

add $1,$1,$2

add $1,$one,$3

add $ane,$1,$4

. . .

In this case, the result is forwarded from the MEM phase because the outcome in the MEM stage is the more recent result. Thus the control for the MEM hazard would be (with the additions highlighted)

if (MEM/WB.RegWrite

and (MEM/WB.RegisterRd _ 0)

and (EX/MEM.RegisterRd _ ID/EX.RegisterRs)

and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01

if (MEM/WB.RegWrite

and (MEM/WB.RegisterRd _ 0)

and (EX/MEM.RegisterRd _ ID/EX.RegisterRt)

and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01

Figure 12.7 shows the datapath modified to resolve hazards via forwarding. Compared with the datapath already shown, the additions are the multiplexors to the inputs to the ALU.

As we already discussed, one instance where forwarding cannot help eliminate hazards is when an instruction tries to read a register following a load instruction that writes the aforementioned register. This is illustrated in Effigy 12.8. The data is still beingness read from retentiveness in clock wheel four while the ALU is performing the operation for the following didactics. Something must stall the pipeline for the combination of load followed by an instruction that reads its result. Hence, in addition to a forwarding unit, we demand a take chances detection unit. It operates during the ID stage and then that it can insert the stall between the load and its use. Checking for load instructions, the control for the hazard detection unit is this single condition:

if (ID/EX.MemRead and

((ID/EX.RegisterRt = IF/ID.RegisterRs) or

(ID/EX.RegisterRt = IF/ID.RegisterRt)))

stall the pipeline

The first line tests to see if the teaching is a load. The only instruction that reads data memory is a load. The adjacent 2 lines check to see if the destination register field of the load in the EX stage matches either source register of the didactics in the ID phase. If the condition holds, the instruction stalls 1 clock cycle. After this one-cycle stall, the forwarding logic can handle the dependence and execution gain. If there were no forwarding, and so the instructions would need another stall wheel.

If the didactics in the ID stage is stalled, then the instruction in the IF stage must also be stalled; otherwise, we would lose the fetched education. Preventing these two instructions from making progress is accomplished simply by preventing the PC register and the IF/ID pipeline register from changing. Provided these registers are preserved, the instruction in the IF stage will go on to exist read using the same PC, and the registers in the ID stage volition continue to be read using the aforementioned instruction fields in the IF/ID pipeline register. The back half of the pipeline starting with the EX phase must exist executing instructions that accept no event. This is done by executing nops. Deasserting all the nine control signals (setting them to 0) in the EX, MEM, and WB stages will create a "do nil" or nop educational activity. Past identifying the hazard in the ID stage, we can insert a chimera into the pipeline past changing the EX, MEM, and WB control fields of the ID/EX pipeline annals to 0. These control values are percolated forward at each clock cycle with the proper event – no registers or memories are written if the command values are all 0.

Figures 12.nine and 12.10 show what really happens in the hardware: the pipeline execution slot associated with the AND instruction is turned into a NOP and all instructions first with the AND instruction are delayed 1 bicycle. The run a risk forces the AND and OR instructions to repeat in clock cycle iv what they did in clock cycle 3: and reads registers and decodes, and OR is refetched from pedagogy retentivity. Such repeated work is what a stall looks like, but its event is to stretch the fourth dimension of the AND and OR instructions and filibuster the fetch of the ADD instruction. Like an air bubble in a water pipe, a stall bubble delays everything behind it and gain down the didactics pipe one stage each cycle until it exits at the end.

Figure 12.11 highlights the pipeline connections for both the hazard detection unit and the forwarding unit of measurement

 Every bit discussed before, the forwarding unit controls the ALU multiplexors to replace the value from a general-purpose register with the value from the proper pipeline annals. The hazard detection unit controls the writing of the PC and IF/ID registers plus the multiplexor that chooses betwixt the real control values and all 0s. The take a chance detection unit stalls and deasserts the control fields if the load-use chance exam is true.

It should be noted that stalls reduce performance, merely are required to go correct results. Also think that the compiler can arrange lawmaking to avert hazards and stalls and information technology requires cognition of the pipeline structure to practice this. For the other types of data hazards, viz. War and WAW hazards where at that place is no true sharing of information, they tin can be resolved past register renaming, which can be handled past the hardware or the compiler. This renaming can happen with retentiveness operands also, which is more than difficultto handle, considering it is difficult to resolve the ambiguity associated with retentiveness operands.

To summarize, in this module nosotros take discussed about how data hazards can be handled by forwarding. This technique requires needs extra hardware paths and control. All cases may not be handled and stalls may be necessary. To avoid War and WAW hazards, annals renaming by software or hardware can be done. RAW hazards can also be handled by reorganization of code, either by software or hardware. The hardware reorganization of code during execution volition exist discussed in afterwards modules.

Web Links / Supporting Materials

• Computer Organization and Pattern – The Hardware / Software Interface, David A. Patterson and John L. Hennessy, 4th.Edition, Morgan Kaufmann, Elsevier, 2009.
• Computer Organization, Carl Hamacher, Zvonko Vranesic and Safwat Zaky, fifth.Edition, McGraw- Hill Higher Education, 2011.

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Source: https://www.cs.umd.edu/~meesh/411/CA-online/chapter/handling-data-hazards/index.html

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